View CD4724BMS_79050.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CD4724BMS
December 1992
CMOS 8-Bit Addressable Latch
Pinout
CD4724BMS TOP VIEW
Features
* High Voltage Type (20V Rating) * Serial Data Input * Active Parallel Output * Storage Register Capability * Master Clear * Can Function as Demultiplexer * Standardized Symmetrical Output Characteristics * 100% Tested for Quiescent Current at 20V * Maximum Input Current of 1A at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC * Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V * 5V, 10V and 15V Parametric Ratings * Meets All Requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of `B' Series CMOS Devices"
A0 A1 A2 Q0 Q1 Q2 Q3 VSS
1 2 3 4 5 6 7 8
16 VDD 15 RESET 14 WRITE DISABLE 13 DATA 12 Q7 11 Q6 10 Q5 9 Q4
Functional Diagram
WRITE DISABLE
14 13
4 5 6 8 LATCHES
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
Applications
* Multi-line Decoders * A/D Converters
DATA 1 A0 A1 A2 2 3 DECODER 8
7 9 10 11
Description
CD4724BMS 8-bit addressable latch is a serial-input, paralleloutput storage register that can perform a variety of functions. Data are inputted to a particular bit in the latch when that bit is addressed (by means of inputs A0, A1, A2) and when WRITE DISABLE is at a low level. When WRITE DISABLE is high, data entry is inhibited; however, all 8 outputs can be continuously read independent of WRITE DISABLE and address inputs. A master RESET input is available, which resets all bits to a logic "0" level when RESET and WRITE DISABLE are at a high level. When RESET is at a high level, and WRITE DISABLE is at a low level, the latch acts as a 1-of-8 demultiplexer; the bit that is addressed has an active output which follows that data input, while all unaddressed bits are held to a logic "0" level. The CD4724BMS is supplied in these 16-lead outline packages: Braze Seal DIP Frit Seal DIP Ceramic Flatpack H4W H1F H6W
RESET VDD = 16 VSS = 8
12
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright (c) Intersil Corporation 1999
File Number
3348
7-1267
Specifications CD4724BMS
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 1/32 Inch (1.59mm 0.79mm) from case for 10s Maximum
Reliability Information
Thermal Resistance . . . . . . . . . . . . . . . . ja jc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W Maximum Package Power Dissipation (PD) at +125oC For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K). . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 1 2 VDD = 18V, VIN = VDD or GND Input Leakage Current IIL VIN = VDD or GND VDD = 20 3 1 2 VDD = 18V Input Leakage Current IIH VIN = VDD or GND VDD = 20 3 1 2 VDD = 18V Output Voltage Output Voltage Output Current (Sink) Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) N Threshold Voltage P Threshold Voltage Functional VOL15 VOH15 IOL5 IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 VNTH VPTH F VDD = 15V, No Load VDD = 15V, No Load (Note 3) VDD = 5V, VOUT = 0.4V VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V VDD = 10V, VOUT = 9.5V VDD = 15V, VOUT = 13.5V VDD = 10V, ISS = -10A VSS = 0V, IDD = 10A VDD = 2.8V, VIN = VDD or GND VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Input Voltage Low (Note 2) Input Voltage High (Note 2) Input Voltage Low (Note 2) Input Voltage High (Note 2) VIL VIH VIL VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V 3 1, 2, 3 1, 2, 3 1 1 1 1 1 1 1 1 1 7 7 8A 8B 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 +25oC, +25oC, LIMITS TEMPERATURE +25oC +125oC -55oC +25oC +125oC -55oC +25oC +125oC -55oC +125oC, +125oC, +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +125oC -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC 3.5 11 1.5 4 V V V V -55oC -55oC MIN -100 -1000 -100 14.95 0.53 1.4 3.5 -2.8 0.7 MAX 10 1000 10 100 1000 100 50 -0.53 -1.8 -1.4 -3.5 -0.7 2.8 UNITS A A A nA nA nA nA nA nA mV V mA mA mA mA mA mA mA V V V
PARAMETER Supply Current
SYMBOL IDD
CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND
VOH > VOL < VDD/2 VDD/2
NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs.
3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max.
7-1268
Specifications CD4724BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS TEMPERATURE 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 TPHL4 TPLH4 TTHL TTLH VDD = 5V, VIN = VDD or GND 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 +25oC +125oC, -55oC LIMITS MIN MAX 400 540 400 540 350 473 450 608 200 270 UNITS ns ns ns ns ns ns ns ns ns ns
PARAMETER Propagation Delay Data to Output Propagation Delay Write Disable to Output Propagation Delay Reset to Output Propagation Delay Address to Output Transition Time
SYMBOL TPHL1 TPLH1 TPHL2 TPLH2 TPHL3
CONDITIONS (NOTE 1, 2) VDD = 5V, VIN = VDD or GND
+25oC +125oC, -55oC
+25oC +125oC, -55oC
+25oC +125oC, -55oC
+25oC +125oC, -55oC
NOTES: 1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS VDD = 5V, VIN = VDD or GND NOTES 1, 2 TEMPERATURE -55oC, +25oC +125oC VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC +125oC VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC +125oC Output Voltage Output Voltage Output Voltage Output Voltage Output Current (Sink) VOL VOL VOH VOH IOL5 VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, VOUT = 0.4V 1, 2 1, 2 1, 2 1, 2 1, 2 +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +125oC -55oC Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125oC -55oC Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC -55oC Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125oC -55oC Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125oC -55oC Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125oC -55oC Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 +125oC -55oC 4.95 9.95 0.36 0.64 0.9 1.6 2.4 4.2 50 -0.36 -0.64 -1.15 -2.0 -0.9 -1.6 -2.4 -4.2 mV V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA MIN MAX 5 150 10 300 10 600 50 UNITS A A A A A A mV
7-1269
Specifications CD4724BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Input Voltage Low Input Voltage High Propagation Delay Data to Output Propagation Delay Write Disable to Output Propagation Delay Reset to Output Propagation Delay Address to Output Transition Time SYMBOL VIL VIH TPHL1 TPLH1 TPHL2 TPLH2 TPHL3 CONDITIONS VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 10V VDD = 15V TPHL4 TPLH4 TTLH TTHL TW VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V Minimum Reset Pulse Width TW VDD = 5V VDD = 10V VDD = 15V Minimum Data Setup Time Data to Write Disable Minimum Data Hold Time Data to Write Disable TS VDD = 5V VDD = 10V VDD = 15V TH VDD = 5V VDD = 10V VDD = 15V Minimum Data Pulse Width TW VDD = 5V VDD = 10V VDD = 15V Input Capacitance NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current N Threshold Voltage N Threshold Voltage Delta SYMBOL IDD VNTH VTN CONDITIONS VDD = 20V, VIN = VDD or GND VDD = 10V, ISS = -10A VDD = 10V, ISS = -10A NOTES 1, 4 1, 4 1, 4 TEMPERATURE +25oC +25oC +25oC MIN -2.8 MAX 25 -0.2 1 UNITS A V V CIN Any Input NOTES 1, 2 1, 2 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2 TEMPERATURE +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC +25 C +25
oC o
MIN +7 -
MAX 3 150 100 160 120 160 130 200 150 100 80 400 200 125 150 75 50 100 50 35 150 75 50 200 100 80 7.5
UNITS V V ns ns ns ns ns ns ns ns ns ns MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns pF
+25oC +25 C +25 C +25oC +25oC +25oC +25oC +25 C +25oC +25oC +25
oC o o o
Minimum Address Pulse Width
+25oC +25 C +25
oC o
+25oC +25
oC
+25oC +25oC +25
oC
+25oC +25oC +25oC +25oC
7-1270
Specifications CD4724BMS
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER P Threshold Voltage P Threshold Voltage Delta Functional SYMBOL VTP VTP F CONDITIONS VSS = 0V, IDD = 10A VSS = 0V, IDD = 10A VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 1, 2, 3, 4 +25oC NOTES 1, 4 1, 4 1 TEMPERATURE +25oC +25oC +25oC MIN 0.2 VOH > VDD/2 MAX 2.8 1 VOL < VDD/2 1.35 x +25oC Limit UNITS V V V
ns
NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
3. See Table 2 for +25oC limit. 4. Read and Record
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC PARAMETER Supply Current - MSI-2 Output Current (Sink) Output Current (Source) SYMBOL IDD IOL5 IOH5A 1.0A 20% x Pre-Test Reading 20% x Pre-Test Reading DELTA LIMIT
TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUP Initial Test (Pre Burn-In) Interim Test 1 (Post Burn-In) Interim Test 2 (Post Burn-In) PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group A Group B Subgroup B-5 Subgroup B-6 Group D MIL-STD-883 METHOD 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 Sample 5005 Sample 5005 Sample 5005 Sample 5005 GROUP A SUBGROUPS 1, 7, 9 1, 7, 9 1, 7, 9 1, 7, 9, Deltas 1, 7, 9 1, 7, 9, Deltas 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas 1, 7, 9 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3 Subgroups 1, 2, 3, 9, 10, 11 IDD, IOL5, IOH5A READ AND RECORD IDD, IOL5, IOH5A IDD, IOL5, IOH5A IDD, IOL5, IOH5A
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION MIL-STD-883 METHOD 5005 TEST PRE-IRRAD 1, 7, 9 POST-IRRAD Table 4 READ AND RECORD PRE-IRRAD 1, 9 POST-IRRAD Table 4
CONFORMANCE GROUPS Group E Subgroup 2
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION Static Burn-In 1 Note 1 OPEN 4 - 7, 9 - 12 GROUND 1 - 3, 8, 13 - 15 VDD 16 9V -0.5V 50kHz 25kHz
7-1271
Specifications CD4724BMS
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION Static Burn-In 2 Note 1 Dynamic BurnIn Note 1 Irradiation Note 2 NOTES: 1. Each pin except VDD and GND will have a series resistor of 10K 5%, VDD = 18V 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V 0.5V OPEN 4 - 7, 9 - 12 4 - 7, 9 - 12 GROUND 8 1 - 3, 8 8 VDD 1 - 3, 13 - 16 16 1 - 3, 13 - 16 4 - 7, 9 - 12 14, 15 13 9V -0.5V 50kHz 25kHz
Logic Diagram
A1 A0 A2 A1 A0 A2 A0 A0 A1 A0 A2 A1 A0 A2 A1 A0 A2 A0 A2 A0 A2 A0 A2 D WD R D WD R D WD R D WD R D WD R D WD R D WD R D WD R LATCH 0 LATCH 1 LATCH 2 LATCH 3 LATCH 4 LATCH 5 LATCH 6 LATCH 7 4 Q0
*
A0 1
5
Q1
6
Q2
*
A1 2 A1 A1
7
Q3
*
A2 3 A2
9
Q4
A1
*
DATA 13
A2 D A1
10
Q5
11
Q6
*
WRITE DISABLE 14 WD
A1
12
Q7
*
RESET 15 R R ADDRESS VSS = 8 VDD = 16 VDD DATA p n Q WD
*ALL INPUTS ARE
PROTECTED BY COS/MOS PROTECTION NETWORK
VSS
p n
FIGURE 1. LOGIC DIAGRAM OF CD4724BMS AND DETAIL OF 1 OF 8 LATCHES
7-1272
CD4724BMS Typical Performance Characteristics
OUTPUT LOW (SINK) CURRENT (IOL) (mA) OUTPUT LOW (SINK) CURRENT (IOL) (mA) AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC
30 25 20 15 10 5
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 7.5 5.0 2.5 10V
10V
5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
FIGURE 2. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V 0
FIGURE 3. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V -5 0
0 -5 -10 -15
0 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
-10V
-20 -25
-10V
-10
-15V
-30
-15V
-15
FIGURE 4. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS
PROPAGATION DELAY TIME (tPLH, tPHL) (ns) AMBIENT TEMPERATURE (TA) = +25oC
FIGURE 5. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS
AMBIENT TEMPERATURE (TA) = +25oC TRANSITION TIME (tTHL, tTLH) (ns)
300 250 200 150 100 50 15V 0 10 20 30 40 50 60 70 80 90 100 10V SUPPLY VOLTAGE (VDD) = 5V
200 SUPPLY VOLTAGE (VDD) = 5V
150
100 10V 50 15V
0 0
20
LOAD CAPACITANCE (CL) (pF)
40 60 80 100 LOAD CAPACITANCE (CL) (pF)
FIGURE 6. TYPICAL PROPAGATION DELAY TIME (DATA TO QN) vs LOAD CAPACITANCE
FIGURE 7. TYPICAL TRANSITION TIME vs LOAD CAPACITANCE
7-1273
CD4724BMS Typical Performance Characteristics
6 4 2 105 6 4 42
(Continued)
AMBIENT TEMPERATURE (TA) = +25oC LOAD CAPACITANCE (CL) = 15pF CL = 50pF
POWER DISSIPATION (PD) (W)
10
6 4 2 103 6 4 22 10 6 4 12
SUPPLY VOLTAGE (VDD) = 15V
5V 10V 10V
10
6 4 02 10 2 4 68
2
4 68
2
4 68
2
4 68
2
4 68
100
101
102 103 104 ADDRESS CYCLE TIME (s)
105
FIGURE 8. TYPICAL DYNAMIC POWER DISSIPATION vs ADDRESS CYCLE TIME
VDD t2 5 4 AST C 1 (t1 < t2) t1 470 pF 7 8 9 12 CD4047 R 2 330 14 8 STARTS CONVERSION 9 1 2 13 10 WD 6 14 OSC OUT 13 R-C 3 1 2 9 10 15 16
VDD
CLOCK CD4520 Q1A Q2A Q3A 3 1 4 2 5 3
R
7
100 K
*
CD4724BMS R 15 DATA Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 4 5 6 7 9 10 11 12 LSB
*
3
12 13
*
VDD 7
11 CD4724BMS OUTPUTS TO DISPLAY 10K 3 2 1 2 3 4 5 6 7 8
5 6
*
4
6
+ CA3130
* CD4001 **HYCOMP HC210SLD - 2R
OR EQUIVALENT 4 5 1 8
MSB
10K 56 pF
16 OUT
R2R LADDER NETWORK ** 9 10 11 12 13
ANALOG IN
100 K
FIGURE 9. A/D CONVERTER
7-1274
CD4724BMS
MODE SELECTION WD 0 0 R 0 1 ADDRESSED LATCH Follows Data Follows Data (Active High 8-Channel Demultiplexer) Holds Previous State Reset to "0" Reset to "0" R = Reset FIGURE 10. DEFINITION OF WRITE DISABLE ON TIME UNADDRESSED LATCH
A0
30% 70%
Holds Previous State Reset to "0"
A1 A2 WD
70% tW
1 1
0 1
WD = Write Disable
A0 A1 A2 A3 DATA IN
1 2 3 14 13
A0 A1 A2 WD DATA CD4724BMS R 15 VDD
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
4 5 6 7 9 10 11 12
D0 D0 D0 D0 D0 D0 D0 D0
1 2 3 4 5 6 7 8
1 2 3 14 13
A0 A1 A2 WD DATA CD4724BMS R 15 VDD
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
4 5 6 7
* *1/6 CD4069
D0 D0 D0 D0 9 D0 10 D0 11 D0 12 D0
9 10 11 12 13 14 15 16
FIGURE 11. 1 OF 16 DECODER/DEMULTIPLEXER
Y IN/OUT 2
CD4724BMS DATA D A0 A1 A2 A3 Q1 Q0
1/4 CD4016 0 1
3
0 S0 S1 S2
WD
R 1 X IN/OUT 2
CD4724BMS D
S5
WD WD
WD
R
Q15
3
FIGURE 12. MULTIPLE SELECTION DECODING - 4 X 4 CROSSPOINT SWITCH
7-1275
CD4724BMS Chip Dimensions and Pad Layout
Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch)
METALLIZATION: PASSIVATION:
Thickness: 11kA - 14kA,
AL.
10.4kA - 15.6kA, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
1276

▲Up To Search▲

Price & Availability of CD4724BMS

	To Download CD4724BMS Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .